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UPSTREAM: superio/nuvoton: Make SuperIO config functions externally available

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TEST=none

Change-Id: I0e7e4ecb909d6f99a1cd1bc965b52694a8291e03
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d84a1cae09
Original-Change-Id: I05f768c67542770e65279a562c05225b84edca40
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/19626
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/506178
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-05-08 21:08:23 +02:00 • committed by chrome-bot
parent 4d30fc943a
commit 09d5220b77
2 changed files with 6 additions and 4 deletions
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8
src/superio/nuvoton/common/early_serial.c
View file

@ -45,7 +45,7 @@
/* Enable configuration: pass entry key '0x87' into index port dev /* Enable configuration: pass entry key '0x87' into index port dev
* two times. */ * two times. */
static void pnp_enter_conf_state(pnp_devfn_t dev) void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev)
{ {
u16 port = dev >> 8; u16 port = dev >> 8;
outb(NUVOTON_ENTRY_KEY, port); outb(NUVOTON_ENTRY_KEY, port);
@ -53,7 +53,7 @@ static void pnp_enter_conf_state(pnp_devfn_t dev)
} }
/* Disable configuration: pass exit key '0xAA' into index port dev. */ /* Disable configuration: pass exit key '0xAA' into index port dev. */
static void pnp_exit_conf_state(pnp_devfn_t dev) void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev)
{ {
u16 port = dev >> 8; u16 port = dev >> 8;
outb(NUVOTON_EXIT_KEY, port); outb(NUVOTON_EXIT_KEY, port);
@ -62,7 +62,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev)
/* Bring up early serial debugging output before the RAM is initialized. */ /* Bring up early serial debugging output before the RAM is initialized. */
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
{ {
pnp_enter_conf_state(dev); nuvoton_pnp_enter_conf_state(dev);
if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A)) if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A))
/* Route GPIO8 pin group to COM A */ /* Route GPIO8 pin group to COM A */
pnp_write_config(dev, 0x2a, 0x40); pnp_write_config(dev, 0x2a, 0x40);
@ -70,5 +70,5 @@ void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
pnp_set_enable(dev, 0); pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1); pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev); nuvoton_pnp_exit_conf_state(dev);
} }

2
src/superio/nuvoton/common/nuvoton.h
View file

@ -21,6 +21,8 @@
#include <arch/io.h> #include <arch/io.h>
#include <stdint.h> #include <stdint.h>
void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev);
void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev);
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase);
#endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ #endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */