Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

UPSTREAM: intel cache-as-ram: Fix comment about MTRRs

Browse source 
Change-Id: I5b9e10fe119c1a046494235e85f730bedfe8578d
Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355002
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-06-21 06:59:30 +03:00 • committed by chrome-bot
parent 3f4d819179
commit 097511eca3
3 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/cpu/intel/car/cache_as_ram.inc
View file

@ -321,8 +321,8 @@ lout:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
/* We don't need CAR from now on. */

4
src/cpu/intel/car/cache_as_ram_ht.inc
View file

@ -342,8 +342,8 @@ no_msr_11e:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
post_code(0x30)

4
src/cpu/intel/model_6ex/cache_as_ram.inc
View file

@ -135,8 +135,8 @@ clear_mtrrs:
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
* after cache-as-ram is torn down.
*/
movl %eax, %ebx
post_code(0x2f)