Emulation/switch-coreboot
1
0
Fork 0
mirror of https://github.com/fail0verflow/switch-coreboot.git synced 2025-05-04 01:39:18 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ

Browse source 
This patch fixes a typo in the clock initialization code that caused the
PERILP1_PCLK_HZ constant to be ignored and the clock to always run at
the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our
previous tests and validation with this bug, we should probably increase
the value of the constant (that had not actually been used) to the value
that we had been incorrectly using instead (which also makes effective
SPI read times faster).

BRANCH=None
BUG=chrome-os-partner:56556
TEST=Booted Kevin.

Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381031
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Julius Werner 2016-09-02 23:48:10 -07:00 • committed by chrome-bot
parent 585ca91f14
commit 06e605a5fc
2 changed files with 4 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
src/soc/rockchip/rk3399/clock.c
View file

@ -477,9 +477,9 @@ void rkclk_init(void)
assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
GPLL_HZ && (hclk_div < 0x1f));
pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
PERILP1_HCLK_HZ && (hclk_div < 0x7));
pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1;
assert((pclk_div + 1) * PERILP1_PCLK_HZ ==
PERILP1_HCLK_HZ && (pclk_div < 0x7));
write32(&cru_ptr->clksel_con[25],
RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK <<

2
src/soc/rockchip/rk3399/include/soc/clock.h
View file

@ -92,7 +92,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE;
#define PERILP0_PCLK_HZ (49500*KHz)
#define PERILP1_HCLK_HZ (99000*KHz)
#define PERILP1_PCLK_HZ (49500*KHz)
#define PERILP1_PCLK_HZ (99000*KHz)
#define PWM_CLOCK_HZ PMU_PCLK_HZ