mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
The m57sli almost builds. It's pretty empty. The dtc is not run .
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Marc Jones <marc.jones@amd.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@702 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich
parent
935c99a3a9
commit
06ced7c09a
13 changed files with 804 additions and 1 deletions
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@ -48,6 +48,14 @@ config CPU_AMD_GEODELX
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_AMD_K8
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config OPTION_TABLE
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boolean
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help
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@ -74,6 +82,7 @@ config CARBASE
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hex
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default 0x8f000 if CPU_I586
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default 0x80000 if CPU_AMD_GEODELX
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default 0xc8000 if CPU_AMD_K8
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help
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This option sets the base address of the area used for CAR.
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@ -81,5 +90,6 @@ config CARSIZE
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hex
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default 0x1000 if CPU_I586
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default 0x8000 if CPU_AMD_GEODELX
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default 0x08000 if CPU_AMD_K8
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help
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This option sets the size of the area used for CAR.
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@ -124,7 +124,10 @@ ifeq ($(CONFIG_CPU_AMD_GEODELX),y)
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STAGE0_ARCH_X86_OBJ += geodelx/stage1.o
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STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o
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else
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STAGE0_CAR_OBJ = stage0_i586.o
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ifeq ($(CONFIG_CPU_AMD_K8),y)
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STAGE0_CAR_OBJ = amd/stage0.o
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STAGE0_ARCH_X86_OBJ += amdk8/stage1.o
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endif
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endif
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endif
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@ -245,6 +248,15 @@ $(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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$(obj)/arch/x86/amd/stage0.o: $(src)/arch/x86/amd/stage0.S
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
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-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
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-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
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$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
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467
arch/x86/amd/stage0.S
Normal file
467
arch/x86/amd/stage0.S
Normal file
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@ -0,0 +1,467 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "../macros.h"
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#define CacheSize DCACHE_RAM_SIZE
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#define CacheBase DCACHE_RAM_BASE
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#define MEM_TOPK 2048
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#define ASSEMBLY
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/* leave some space for global variable to pass to RAM stage */
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#define GlobalVarSize 32
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#ifdef CONFIG_CPU_AMD_K10
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#define CacheSizeAPStack 0x400 /* 1K */
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#endif
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#include <mtrr.h>
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#include <amd_k8.h>
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.code16
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.globl _stage0
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_stage0:
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cli
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/* Save the BIST result. */
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movl %eax, %ebp;
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/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
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* executing any further code. Even though paging is disabled we
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* could still get false address translations due to the TLB if we
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* didn't invalidate it.
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*/
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xorl %eax, %eax
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movl %eax, %cr3 /* Invalidate TLB. */
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/* Switch to protected mode. */
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/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
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* using BFD version 2.15.94.0.2.2 20041220 this works fine without
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* all the ld hackery and so on. So leave it as is with this comment.
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*/
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data32 lgdt %cs:gdtptr
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movl %cr0, %eax
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andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
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orl $0x60000001, %eax /* CD, NW, PE = 1 */
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movl %eax, %cr0
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/* Restore BIST result. */
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movl %ebp, %eax
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// port80_post(0x23)
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/* Now we are in protected mode. Jump to a 32 bit code segment. */
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data32 ljmp $ROM_CODE_SEG, $protected_stage0
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/* I am leaving this weird jump in here in the event that future gas
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* bugs force it to be used.
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*/
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/* .byte 0x66 */
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.code32
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/* ljmp $ROM_CODE_SEG, $protected_stage0 */
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/* .code16 */
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.align 4
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.globl gdt16
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gdt16 = . - _stage0
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gdt16x:
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.word gdt16xend - gdt16x -1 /* Compute the table limit. */
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.long gdt16x
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt16xend:
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/* From now on we are 32bit. */
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.code32
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/* We have two gdts where we could have one. That is ok.
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*
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* Let's not worry about this -- optimizing gdt is pointless since
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* we're only in it for a little bit.
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*
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* Btw. note the trick below: The GDT points to ITSELF, and the first
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* good descriptor is at offset 8. So you word-align the table, and
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* then because you chose 8, you get a nice 64-bit aligned GDT entry,
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* which is good as this is the size of the entry.
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*
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* Just in case you ever wonder why people do this.
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*/
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.align 4
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.globl gdtptr
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.globl gdt_limit
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gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
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gdt:
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gdtptr:
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.word gdt_end - gdt -1 /* Compute the table limit. */
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.long gdt /* We know the offset. */
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.word 0
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/* selgdt 0x08, flat code segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x10, flat data segment */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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/* selgdt 0x18, flat code segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x9b, 0xcf, 0x00
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/* selgdt 0x20, flat data segment for CAR */
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.word 0xffff, 0x0000
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.byte 0x00, 0x93, 0xcf, 0x00
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gdt_end:
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/* When we come here we are in protected mode. We expand the stack
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* and copy the data segment from ROM to the memory.
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*
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* After that, we call the chipset bootstrap routine that
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* does what is left of the chipset initialization.
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*
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* Note: Aligned to 4 so that we are sure that the prefetch
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* cache will be reloaded.
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*/
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.align 4
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.globl protected_stage0
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protected_stage0:
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/* This code was used by v2. TODO. */
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lgdt %cs:gdtptr
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ljmp $ROM_CODE_SEG, $__protected_stage0
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.globl __protected_stage0
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__protected_stage0:
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/* Save the BIST result */
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movl %eax, %ebp
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/*for normal part %ebx already contain cpu_init_detected from fallback call */
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cache_as_ram_setup:
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movb $0xA0, %al
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outb %al, $0x80
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/* check if cpu_init_detected */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(1 << 11), %eax
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movl %eax, %ebx /* We store the status */
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#ifdef CONFIG_CPU_AMD_K10
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/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
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/* Only BSP needed, for other nodes set during HT/memory init. */
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/* So we need to check if it is BSP */
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movl $0x1b, %ecx
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rdmsr
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bt $8, %eax /*BSC */
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jnc CAR_FAM10_out
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/* Enable RT tables on BSP */
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movl $0x8000c06c, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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addw $4, %dx
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inl %dx, %eax
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btr $0, %eax
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outl %eax, %dx
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/* Setup temporary DRAM map: [0,16M) bit 0-23 */
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movl $0x8000c144, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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addw $4, %dx
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movl $0, %eax
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outl %eax, %dx
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movl $0x8000c140, %eax
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movw $0xcf8, %dx
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outl %eax, %dx
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addw $4, %dx
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movl $3, %eax
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outl %eax, %dx
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CAR_FAM10_out:
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#endif
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#ifdef CONFIG_CPU_AMD_K10
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/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
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Re-enable it in after RAM is initialized and before CAR is disabled */
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movl $0xc001102a, %ecx
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rdmsr
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bts $15, %eax
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wrmsr
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#endif
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/* Set MtrrFixDramModEn for clear fixed mtrr */
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enable_fixed_mtrr_dram_modify:
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movl $SYSCFG_MSR, %ecx
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rdmsr
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andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
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orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
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wrmsr
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/* Clear all MTRRs */
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xorl %edx, %edx
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movl $fixed_mtrr_msr, %esi
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clear_fixed_var_mtrr:
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lodsl (%esi), %eax
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testl %eax, %eax
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jz clear_fixed_var_mtrr_out
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movl %eax, %ecx
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xorl %eax, %eax
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wrmsr
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jmp clear_fixed_var_mtrr
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clear_fixed_var_mtrr_out:
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/* 0x06 is the WB IO type for a given 4k segment.
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* 0x1e is the MEM IO type for a given 4k segment (K10 and above).
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* segs is the number of 4k segments in the area of the particular
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* register we want to use for CAR.
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* reg is the register where the IO type should be stored.
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*/
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.macro extractmask segs, reg
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.if \segs <= 0
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/* The xorl here is superfluous because at the point of first execution
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* of this macro, %eax and %edx are cleared. Later invocations of this
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* macro will have a monotonically increasing segs parameter.
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*/
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xorl \reg, \reg
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#ifdef CONFIG_CPU_AMD_K10
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.elseif \segs == 1
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movl $0x1e000000, \reg /* WB MEM type */
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.elseif \segs == 2
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movl $0x1e1e0000, \reg /* WB MEM type */
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.elseif \segs == 3
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movl $0x1e1e1e00, \reg /* WB MEM type */
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.elseif \segs >= 4
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movl $0x1e1e1e1e, \reg /* WB MEM type */
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#else
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.elseif \segs == 1
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movl $0x06000000, \reg /* WB IO type */
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.elseif \segs == 2
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movl $0x06060000, \reg /* WB IO type */
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.elseif \segs == 3
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movl $0x06060600, \reg /* WB IO type */
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.elseif \segs >= 4
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movl $0x06060606, \reg /* WB IO type */
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#endif
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.endif
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.endm
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/* size is the cache size in bytes we want to use for CAR.
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* windowoffset is the 32k-aligned window into CAR size
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*/
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.macro simplemask carsize, windowoffset
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.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
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extractmask gas_bug_workaround, %eax
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.set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
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extractmask gas_bug_workaround, %edx
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/* Without the gas bug workaround, the entire macro would consist only of the
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* two lines below.
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extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
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extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
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*/
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.endm
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#if CacheSize > 0x10000
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#error Invalid CAR size, must be at most 64k.
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#endif
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#if CacheSize < 0x1000
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#endif
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#if (CacheSize & (0x1000 - 1))
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#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
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#endif
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#if CacheSize > 0x8000
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/* enable caching for 32K-64K using fixed mtrr */
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movl $0x268, %ecx /* fix4k_c0000*/
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simplemask CacheSize, 0x8000
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wrmsr
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#endif
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/* enable caching for 0-32K using fixed mtrr */
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movl $0x269, %ecx /* fix4k_c8000*/
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simplemask CacheSize, 0
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wrmsr
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/* enable memory access for first MBs using top_mem */
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movl $TOP_MEM, %ecx
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xorl %edx, %edx
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movl $(((MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
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wrmsr
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/* disable cache */
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movl %cr0, %eax
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orl $(1 << 30),%eax
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movl %eax, %cr0
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/* this seems safe to do always. Leave it for now. */
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/*#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))*/
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/* Set the default memory type and enable fixed and variable MTRRs */
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movl $MTRRdefType_MSR, %ecx
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xorl %edx, %edx
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/* Enable Variable and Fixed MTRRs */
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movl $0x00000c00, %eax
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wrmsr
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/* Enable the MTRRs and IORRs in SYSCFG */
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movl $SYSCFG_MSR, %ecx
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rdmsr
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orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
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wrmsr
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movb $0xA1, %al
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outb %al, $0x80
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/* enable cache */
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movl %cr0, %eax
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andl $0x9fffffff, %eax
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movl %eax, %cr0
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||||
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||||
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||||
#ifdef CONFIG_CPU_AMD_K10
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/* So we need to check if it is BSP */
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movl $0x1b, %ecx
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rdmsr
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bt $8, %eax /*BSC */
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jnc CAR_FAM10_ap
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#endif
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movb $0xA2, %al
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outb %al, $0x80
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/*#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))*/
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/* Read the range with lodsl*/
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cld
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movl $CacheBase, %esi
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movl $(CacheSize >> 2), %ecx
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rep lodsl
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/* Clear the range */
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movl $CacheBase, %edi
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movl $(CacheSize >> 2), %ecx
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xorl %eax, %eax
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rep stosl
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||||
//#endif /*USE_FAILOVER_IMAGE == 1*/
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||||
/* set up the stack pointer */
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movl $(CacheBase + CacheSize - GlobalVarSize), %eax
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||||
movl %eax, %esp
|
||||
|
||||
movb $0xA3, %al
|
||||
outb %al, $0x80
|
||||
|
||||
#ifdef CONFIG_CPU_AMD_K10
|
||||
|
||||
jmp CAR_FAM10_ap_out
|
||||
CAR_FAM10_ap:
|
||||
/* need to set stack pointer for AP */
|
||||
/* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/
|
||||
/* So need to get the NodeID and CoreID at first */
|
||||
/* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */
|
||||
|
||||
/* store our init detected */
|
||||
movl %ebx, %esi
|
||||
|
||||
/* get the coreid bits at first */
|
||||
movl $0x80000008, %eax
|
||||
cpuid
|
||||
shrl $12, %ecx
|
||||
andl $0x0f, %ecx
|
||||
movl %ecx, %edi
|
||||
|
||||
/* get the initial apic id */
|
||||
movl $1, %eax
|
||||
cpuid
|
||||
shrl $24, %ebx
|
||||
|
||||
/* get the nb cfg bit 54 */
|
||||
movl $0xc001001f, %ecx /* NB_CFG_MSR */
|
||||
rdmsr
|
||||
movl %edi, %ecx /* CoreID bits */
|
||||
bt $(54-32), %edx
|
||||
jc roll_cfg
|
||||
rolb %cl, %bl
|
||||
roll_cfg:
|
||||
|
||||
/* calculate stack pointer */
|
||||
movl $CacheSizeAPStack, %eax
|
||||
mull %ebx
|
||||
movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp
|
||||
subl %eax, %esp
|
||||
|
||||
/* retrive init detected */
|
||||
movl %esi, %ebx
|
||||
|
||||
movb $0xA4, %al
|
||||
outb %al, $0x80
|
||||
|
||||
CAR_FAM10_ap_out:
|
||||
#endif
|
||||
|
||||
movb $0xA5, %al
|
||||
outb %al, $0x80
|
||||
|
||||
/* Restore the BIST result */
|
||||
movl %ebp, %eax
|
||||
|
||||
/* We need to set ebp ? No need */
|
||||
movl %esp, %ebp
|
||||
pushl %ebx /* init detected */
|
||||
pushl %eax /* bist */
|
||||
call stage1_main
|
||||
/* We will not go back */
|
||||
|
||||
movb $0xAF, %al /* Should never see this postcode */
|
||||
outb %al, $0x80
|
||||
|
||||
fixed_mtrr_msr:
|
||||
.long 0x250, 0x258, 0x259
|
||||
.long 0x268, 0x269, 0x26A
|
||||
.long 0x26B, 0x26C, 0x26D
|
||||
.long 0x26E, 0x26F
|
||||
var_mtrr_msr:
|
||||
.long 0x200, 0x201, 0x202, 0x203
|
||||
.long 0x204, 0x205, 0x206, 0x207
|
||||
.long 0x208, 0x209, 0x20A, 0x20B
|
||||
.long 0x20C, 0x20D, 0x20E, 0x20F
|
||||
var_iorr_msr:
|
||||
.long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
|
||||
mem_top:
|
||||
.long 0xC001001A, 0xC001001D
|
||||
.long 0x000 /* NULL, end of table */
|
||||
|
||||
cache_as_ram_setup_out:
|
||||
42
arch/x86/amdk8/stage1.c
Normal file
42
arch/x86/amdk8/stage1.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
#include <msr.h>
|
||||
#include <amd_k8.h>
|
||||
|
||||
/**
|
||||
* Disable Cache As RAM (CAR) after memory is setup.
|
||||
*
|
||||
* Unknown how to do this just yet.
|
||||
*/
|
||||
void disable_car(void)
|
||||
{
|
||||
/* OK, here is the theory: we should be able to copy
|
||||
* the data back over itself, and the wbinvd should then
|
||||
* flush to memory. Let's see.
|
||||
*/
|
||||
__asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
|
||||
__asm__ __volatile__ ("wbinvd\n");
|
||||
banner(BIOS_DEBUG, "Disable_car: done wbinvd");
|
||||
banner(BIOS_DEBUG, "disable_car: done");
|
||||
}
|
||||
56
include/arch/x86/amd_k8.h
Normal file
56
include/arch/x86/amd_k8.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#define ROM_CODE_SEG 0x08
|
||||
#define ROM_DATA_SEG 0x10
|
||||
|
||||
#define CACHE_RAM_CODE_SEG 0x18
|
||||
#define CACHE_RAM_DATA_SEG 0x20
|
||||
|
||||
#define IORR_FIRST 0xC0010016
|
||||
#define IORR_LAST 0xC0010019
|
||||
|
||||
#define MTRR_READ_MEM (1 << 4)
|
||||
#define MTRR_WRITE_MEM (1 << 3)
|
||||
|
||||
#define SYSCFG_MSR 0xC0010010
|
||||
#define SYSCFG_MSR_TOM2En (1 << 21)
|
||||
#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
|
||||
#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
|
||||
#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
|
||||
#define SYSCFG_MSR_UcLockEn (1 << 17)
|
||||
#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
|
||||
#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
|
||||
#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
|
||||
#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
|
||||
#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
|
||||
#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
|
||||
#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
|
||||
|
||||
#define IORR0_BASE 0xC0010016
|
||||
#define IORR0_MASK 0xC0010017
|
||||
#define IORR1_BASE 0xC0010018
|
||||
#define IORR1_MASK 0xC0010019
|
||||
#define TOP_MEM 0xC001001A
|
||||
#define TOP_MEM2 0xC001001D
|
||||
|
||||
#define TOP_MEM_MASK 0x007fffff
|
||||
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
|
||||
|
||||
|
||||
|
|
@ -42,6 +42,11 @@ config VENDOR_ARTECGROUP
|
|||
help
|
||||
Select this option for various systems from the Artec Group.
|
||||
|
||||
config VENDOR_GIGABYTE
|
||||
bool "Gigabyte"
|
||||
help
|
||||
Select this option for various systems from Gigabyte
|
||||
|
||||
config VENDOR_EMULATION
|
||||
bool "Emulated systems"
|
||||
help
|
||||
|
|
@ -58,6 +63,7 @@ source "mainboard/adl/Kconfig"
|
|||
source "mainboard/amd/Kconfig"
|
||||
source "mainboard/artecgroup/Kconfig"
|
||||
source "mainboard/emulation/Kconfig"
|
||||
source "mainboard/gigabyte/Kconfig"
|
||||
source "mainboard/pcengines/Kconfig"
|
||||
|
||||
choice
|
||||
|
|
|
|||
36
mainboard/gigabyte/Kconfig
Normal file
36
mainboard/gigabyte/Kconfig
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 coresystems GmbH
|
||||
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
depends on VENDOR_GIGABYTE
|
||||
|
||||
config BOARD_GIGABYTE_M57SLI
|
||||
bool "M57SLI"
|
||||
select ARCH_X86
|
||||
select OPTION_TABLE
|
||||
select CPU_AMD_K8
|
||||
help
|
||||
Gigabyte M57SLI
|
||||
|
||||
endchoice
|
||||
|
||||
source "mainboard/gigabyte/m57sli/Kconfig"
|
||||
28
mainboard/gigabyte/m57sli/Kconfig
Normal file
28
mainboard/gigabyte/m57sli/Kconfig
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 coresystems GmbH
|
||||
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
|
||||
## Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
config MAINBOARD_NAME
|
||||
string
|
||||
default gigabyte/m57sli
|
||||
depends BOARD_GIGABYTE_M57SLI
|
||||
help
|
||||
This is the default mainboard name.
|
||||
31
mainboard/gigabyte/m57sli/Makefile
Normal file
31
mainboard/gigabyte/m57sli/Makefile
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2006-2007 coresystems GmbH
|
||||
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
|
||||
|
||||
INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c
|
||||
|
||||
STAGE2_MAINBOARD_OBJ =
|
||||
|
||||
$(obj)/coreboot.vpd:
|
||||
$(Q)printf " BUILD DUMMY VPD\n"
|
||||
$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
|
||||
|
||||
29
mainboard/gigabyte/m57sli/dts
Normal file
29
mainboard/gigabyte/m57sli/dts
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/{
|
||||
mainboard_vendor = "Gigabyte";
|
||||
mainboard_name = "M57SLI";
|
||||
cpus { };
|
||||
apic@0 {
|
||||
};
|
||||
domain@0 {
|
||||
};
|
||||
};
|
||||
45
mainboard/gigabyte/m57sli/initram.c
Normal file
45
mainboard/gigabyte/m57sli/initram.c
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2007 Ronald G. Minnich
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define _MAINOBJECT
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <msr.h>
|
||||
#include <io.h>
|
||||
#include <amd_k8.h>
|
||||
#include <spd.h>
|
||||
|
||||
/**
|
||||
* main for initram for the Gigabyte m57sli.
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Hi there from stage1\n");
|
||||
post_code(POST_START_OF_MAIN);
|
||||
|
||||
printk(BIOS_DEBUG, "stage1 returns\n");
|
||||
return 0;
|
||||
}
|
||||
41
mainboard/gigabyte/m57sli/stage1.c
Normal file
41
mainboard/gigabyte/m57sli/stage1.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2008 Ronald G. Minnich
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <lib.h>
|
||||
#include <console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <msr.h>
|
||||
#include <io.h>
|
||||
#include <arch/x86/msr.h>
|
||||
|
||||
void hardware_stage1(void)
|
||||
{
|
||||
post_code(POST_START_OF_MAIN);
|
||||
|
||||
}
|
||||
|
||||
void mainboard_pre_payload(void)
|
||||
{
|
||||
banner(BIOS_DEBUG, "mainboard_pre_payload: done");
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue