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UPSTREAM: intel post-car: Split legacy sockets
Move old sockets to use romstage_legacy.c, these are ones using intel/car/cache_as_ram.inc. These will not be converted to RELOCATABLE_RAMSTAGE as boards are candidates for getting dropped from the tree anyways. BUG=None BRANCH=None TEST=None Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb Reviewed-on: https://chromium-review.googlesource.com/408983 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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6 changed files with 25 additions and 5 deletions
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src/cpu/intel/car/romstage_legacy.c
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src/cpu/intel/car/romstage_legacy.c
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@ -0,0 +1,20 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/intel/romstage.h>
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void * asmlinkage romstage_main(unsigned long bist)
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{
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mainboard_romstage_entry(bist);
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return (void*)CONFIG_RAMTOP;
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}
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@ -29,4 +29,4 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../microcode
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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romstage-y += ../car/romstage.c
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romstage-y += ../car/romstage_legacy.c
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@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../microcode
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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romstage-y += ../car/romstage.c
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romstage-y += ../car/romstage_legacy.c
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@ -23,4 +23,4 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../microcode
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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romstage-y += ../car/romstage.c
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romstage-y += ../car/romstage_legacy.c
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@ -7,4 +7,4 @@ subdirs-y += ../../x86/smm
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subdirs-y += ../microcode
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subdirs-y += ../microcode
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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romstage-y += ../car/romstage.c
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romstage-y += ../car/romstage_legacy.c
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@ -10,4 +10,4 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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subdirs-y += ../hyperthreading
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
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romstage-y += ../car/romstage.c
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romstage-y += ../car/romstage_legacy.c
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