mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
Changed
option SERIAL_CONSOLE to option SERIAL_CONSOLE=1
This commit is contained in:
parent
45c7f99fe8
commit
0222d47c61
18 changed files with 18 additions and 18 deletions
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@ -1,6 +1,6 @@
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#include <logbuf_subr.h>
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#include <logbuf_subr.h>
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#define LOGBUF_SIZE = 1024;
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#define LOGBUF_SIZE 1024
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// KEEP THIS GLOBAL.
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// KEEP THIS GLOBAL.
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// I need the address so I can watch it with the ARIUM hardware. RGM.
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// I need the address so I can watch it with the ARIUM hardware. RGM.
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@ -13,7 +13,7 @@ option USE_DOC_MIL
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docipl mainboard/asus/cua/ipl.S
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docipl mainboard/asus/cua/ipl.S
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -13,7 +13,7 @@ option USE_DOC_MIL
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docipl northbridge/acer/m1631/ipl.S
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docipl northbridge/acer/m1631/ipl.S
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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#option UPDATE_MICROCODE
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#option UPDATE_MICROCODE
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@ -7,7 +7,7 @@ target ga-6bxc
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mainboard gigabit/ga-6bxc
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mainboard gigabit/ga-6bxc
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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option NO_KEYBOARD
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option NO_KEYBOARD
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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@ -7,7 +7,7 @@ target proto1
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mainboard irobot/proto1
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mainboard irobot/proto1
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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option NO_KEYBOARD
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option NO_KEYBOARD
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# Enable MicroCode update for PIII
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# Enable MicroCode update for PIII
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@ -2,7 +2,7 @@ target purple_box
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mainboard lanner/em-370
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mainboard lanner/em-370
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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option SERIAL_POST
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option SERIAL_POST
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#option HAVE_FAMEBUFFER
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#option HAVE_FAMEBUFFER
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@ -7,7 +7,7 @@ mainboard matsonic/ms7308e
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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#option UPDATE_MICROCODE
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#option UPDATE_MICROCODE
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@ -8,7 +8,7 @@ mainboard pcchips/m810lmr
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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#option UPDATE_MICROCODE
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#option UPDATE_MICROCODE
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@ -8,7 +8,7 @@ mainboard rcn/dc1100s
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option USE_DOC_MIL
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option USE_DOC_MIL
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docipl northbridge/via/vt694/ipl.S
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docipl northbridge/via/vt694/ipl.S
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -5,7 +5,7 @@ target tlsbc710
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mainboard technoland/sbc710
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mainboard technoland/sbc710
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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option NO_KEYBOARD
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option NO_KEYBOARD
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option INBUF_COPY
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option INBUF_COPY
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@ -7,7 +7,7 @@ mainboard tyan/s1846
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -68,6 +68,6 @@ makerule Specify an additional makerule, e.g.
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commandline Specify the command line, e.g.
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commandline Specify the command line, e.g.
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commandline root=/dev/hda1 single
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commandline root=/dev/hda1 single
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option Add an option, implicitly setting it.
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option Add an option, implicitly setting it.
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e.g. option SERIAL_CONSOLE
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e.g. option SERIAL_CONSOLE=1
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@ -6,7 +6,7 @@ target asus_cua
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mainboard asus/cua
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mainboard asus/cua
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -7,7 +7,7 @@ mainboard compaq/ds10
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable SROM_CONSOLE
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# Enable SROM_CONSOLE
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# This uses the SROM serial debug port at 9600 baud
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# This uses the SROM serial debug port at 9600 baud
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@ -6,7 +6,7 @@ mainboard intel/l440bx
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -7,7 +7,7 @@ mainboard intel/l440gx
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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# It will come up at 115200,8n1
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# It will come up at 115200,8n1
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -6,7 +6,7 @@ target vt5292
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mainboard via/vt5292
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mainboard via/vt5292
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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@ -8,7 +8,7 @@ mainboard via/vt5426
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option USE_DOC_MIL
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option USE_DOC_MIL
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docipl northbridge/via/vt8601/ipl.S
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docipl northbridge/via/vt8601/ipl.S
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# Enable Serial Console for debugging
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# Enable Serial Console for debugging
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option SERIAL_CONSOLE
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option SERIAL_CONSOLE=1
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# Enable MicroCode update and L2 Cache init for PII and PIII
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# Enable MicroCode update and L2 Cache init for PII and PIII
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option UPDATE_MICROCODE
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option UPDATE_MICROCODE
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