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UPSTREAM: soc/apollolake: Use simpler macros for the northbridge PCI device

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The NB_DEV_ROOT macro, is almost unreadable, as it depends on other
stringified macros, and acts differently depending on the coreboot
stage. For ramstage, it also hides a function call.
Rewrite the macro in terms of more basic and readable macros.

BUG=None
BRANCH=None
TEST=None

Change-Id: I9b7071d67c8d58926e9b01fadaa239db1120448c
Original-Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Original-Reviewed-on: https://review.coreboot.org/14890
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347587
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Alexandru Gagniuc 2016-05-18 10:26:53 -07:00 • committed by chrome-bot
parent 6051fff969
commit 016716542f
2 changed files with 4 additions and 10 deletions
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2
src/soc/intel/apollolake/chip.c
View file

@ -100,7 +100,7 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
struct device *dev = NB_DEV_ROOT;
struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;

12
src/soc/intel/apollolake/include/soc/pci_devs.h
View file

@ -17,26 +17,17 @@
#include <rules.h>
#define _NB_DEVFN(slot) PCI_DEVFN(NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func)
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#include <device/pci_def.h>
#define _NB_DEV(slot) dev_find_slot(0, _NB_DEVFN(slot))
#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, func))
#else
#include <arch/io.h>
#define _NB_DEV(slot) PCI_DEV(0, NB_DEV_SLOT_ ## slot, 0)
#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func)
#endif
/* North bridge devices */
#define NB_DEV_SLOT_ROOT 0x00
#define NB_DEVFN_ROOT _NB_DEVFN(ROOT)
#define NB_DEV_ROOT _NB_DEV(ROOT)
/* LPSS UART */
#define LPSS_DEV_SLOT_UART 0x18
#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0)
@ -48,6 +39,9 @@
#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2)
#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3)
#define NB_BUS 0
#define NB_DEVFN PCI_DEVFN(0, 0)
#define NB_DEV_ROOT PCI_DEV(NB_BUS, 0x0, 0)
#define P2SB_DEV PCI_DEV(0, 0xd, 0)
#define PMC_DEV PCI_DEV(0, 0xd, 1)
#define SPI_DEV PCI_DEV(0, 0xd, 2)