mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
UPSTREAM: soc/intel/common/block/cse: Add GLK PCI ID
BUG=none
BRANCH=none
TEST=none
Change-Id: Iade7f4f28f2a8148e4e70f5b5d0948252cfbec82
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 63142153ba
Original-Change-Id: I88e376d61c4aba5030a0be7c8bdfe7b57881a197
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://review.coreboot.org/20169
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/539226
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
parent
7ccfc8a705
commit
000f6a18ce
1 changed files with 7 additions and 1 deletions
|
@ -465,11 +465,17 @@ static struct device_operations cse_ops = {
|
|||
.init = pci_dev_init,
|
||||
};
|
||||
|
||||
static const unsigned short pci_device_ids[] = {
|
||||
PCI_DEVICE_ID_INTEL_APL_CSE0,
|
||||
PCI_DEVICE_ID_INTEL_GLK_CSE0,
|
||||
0,
|
||||
};
|
||||
|
||||
static const struct pci_driver cse_driver __pci_driver = {
|
||||
.ops = &cse_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
/* SoC/chipset needs to provide PCI device ID */
|
||||
.device = PCI_DEVICE_ID_INTEL_APL_CSE0,
|
||||
.devices = pci_device_ids,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Add table
Reference in a new issue