##
## Config file for the Embedded Planet EP405PC Computing Engine
##

uses PCIC0_CFGADDR 
uses CONFIG_CBFS
uses PCIC0_CFGDATA 
uses ISA_IO_BASE 
uses ISA_MEM_BASE 
uses TTYS0_BASE 
uses _IO_BASE 

uses CPU_OPT
uses CROSS_COMPILE 
uses HAVE_OPTION_TABLE
uses CONFIG_COMPRESS 
uses CONFIG_CHIP_CONFIGURE
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_USE_INIT
uses CONFIG_CONSOLE_SERIAL8250 
uses TTYS0_BAUD TTYS0_DIV
uses NO_POST
uses CONFIG_IDE
uses CONFIG_FS_PAYLOAD
uses CONFIG_FS_EXT2
uses CONFIG_FS_ISO9660
uses CONFIG_FS_FAT
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
uses AUTOBOOT_CMDLINE
uses CONFIG_SYS_CLK_FREQ
uses IDE_BOOT_DRIVE
#uses IDE_SWAB
uses IDE_OFFSET 
uses ROM_SIZE
uses ROM_IMAGE_SIZE
uses _RESET
uses _EXCEPTION_VECTORS
uses _ROMBASE
uses _ROMSTART
uses _RAMBASE
#uses _RAMSTART
uses EMBEDDED_RAM_SIZE
uses STACK_SIZE HEAP_SIZE

uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
uses COREBOOT_EXTRA_VERSION
uses CROSS_COMPILE
uses CC
uses HOSTCC
uses OBJCOPY

##
## Set PCI configuration register addresses
##
default PCIC0_CFGADDR=0xeec00000
default PCIC0_CFGDATA=0xeec00004

##
## Set PCI/ISA I/O and memory base address
##
default ISA_IO_BASE=0xe8000000
default ISA_MEM_BASE=0x80000000
default _IO_BASE=ISA_IO_BASE

##
## HACK ALERT: the UART0 registers are not in the PCI I/O address space
## but both IDE and UART use the same routines for I/O (inb/outb). To get 
## around this we set TTYSO_BASE to the difference between the two.
##
default TTYS0_BASE=0xef600300-ISA_IO_BASE

## Enable PPC405 instructions
default CPU_OPT="-mcpu=405"
#default CPU_OPT=""

## Use stage 1 initialization code
default CONFIG_USE_INIT=1

## Use chip configuration
default CONFIG_CHIP_CONFIGURE=1

## We don't use compressed image
default CONFIG_COMPRESS=0

## Turn off POST codes
default NO_POST=1

## Enable serial console
default DEFAULT_CONSOLE_LOGLEVEL=8
default CONFIG_CONSOLE_SERIAL8250=1
# Divisor of 69 == 9600 baud due to weird clocking
default TTYS0_DIV=69
default TTYS0_BAUD=9600

## Boot linux from IDE
default CONFIG_IDE=1
default CONFIG_FS_PAYLOAD=1
default CONFIG_FS_EXT2=1
default CONFIG_FS_ISO9660=1
default CONFIG_FS_FAT=1
default AUTOBOOT_CMDLINE="hda1:/vmlinuz"

default ROM_SIZE=1048576

## Board has fixed size RAM
default EMBEDDED_RAM_SIZE=64*1024*1024

## Coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000

##
## Use a 64K stack
##
default STACK_SIZE=0x10000

##
## Use a 64K heap
##
default HEAP_SIZE=0x10000

##
## System clock
##
default CONFIG_SYS_CLK_FREQ=33

##
default _ROMBASE=0xfff00000

## Reset vector address
default _RESET=0xfffffffc

## Exception vectors
default _EXCEPTION_VECTORS=_ROMBASE+0x100

## coreboot ROM start address
default _ROMSTART=0xfff03000

## coreboot C code runs at this location in RAM
default _RAMBASE=0x00100000

### End Options.lb
#
# CBFS
#
#
default CONFIG_CBFS=0
end
